COMPUTER ARCHITECTURE
COMPUTER ARCHITECTURE:
INTERNET PROTOCOL-IP (CS)
MULTIPLE ISSUE PROCESSORS I
MULTIPLE ISSUE PROCESSORS II
THREAD LEVEL PARALLELISM – SMT AND CMP
COMPUTER ARCHITECTURE: INTRODUCTION
INSTRUCTION SET ARCHITECTURE
PERFORMANCE METRICS
SUMMARIZING PERFORMANCE, AMDHALS LAW AND BENCHMARKS
FIXED POINT ARITHMETIC-UNIT I
FIXED POINT ARITHMETIC-UNIT II
FLOATING POINT ARITHMETIC-UNIT
EXECUTION OF COMPLETE INSTRUCTION: DATAPATH IMPLEMENTATION
EXECUTION OF COMPLETE INSTRUCTION: CONTROL FLOW
PIPELINING: MIPS IMPLEMENTATION
PIPELINE HAZARDS
HANDLING DATA HAZARDS
HANDLING CONTROL HAZARDS
DYNAMIC BRANCH PREDICTION
EXCEPTION HANDLING AND FLOATING POINT PIPELINES
ADVANCED CONCEPTS OF ILP - DYNAMIC SCHEDULING
DYNAMIC SCHEDULING EXAMPLE
DYNAMIC SCHEDULING -LOOP BASED EXAMPLE
DYANAMIC SCHEDULING WITH SPECULATION
EXPLOITING ILP WITH SOFTWARE APPROACHES I
VIRTUAL MEMORY I
VIRTUAL MEMORY 2
CACHE COHERENCE I
CACHE COHERENCE II
CACHE COHERENCE III
OTHER ISSUES WITH PARALLEL PROCESSORS
EXPLOITING DATA LEVEL PARALLELISM
INTRODUCTION TO MULTIPROCESSORS